1. Field of the Invention
This invention pertains to the general field of track-and-hold and sample-and-hold amplifiers. In particular, it provides a new track-and-hold amplifier circuit which utilizes the phase compensation capacitors of standard operational amplifier configurations as hold capacitors in the hold mode of operation.
2. Description of the Prior Art
The general purpose of track-and-hold amplifiers is to accurately track an analog input signal and, at specified times, to accurately hold at its output for a certain length of time the instantaneous value of the input signal. This form of signal conditioning is particularly important ahead of multi-step analog-to-digital converters, where the quality of conversion is greatly improved by maintaining a substantially constant value at the input of the analog-to-digital converter for any given analog signal. The speed-accuracy product of multistep analog-to-digital conversion can be increased by orders of magnitude with the appropriate sample-and-hold circuitry. Thus, the varying analog signal is tracked and a succession of its values at selected intervals is held constant for conversion to digital representation by the analog-to-digital converter. Track-and-hold and sample-and-hold devices perform essentially the same function, but the sample time is arbitrarily long in the former while it is short and fixed in the latter. Therefore, a track-and-hold device can generally be used as a sample-and-hold apparatus, but not necessarily vice versa.
Conventional track-and-hold circuits typically surround switching circuits and hold capacitors with one or more amplifiers. Within this general description, various topologies have been developed to improve the performance of each circuit for specific applications. For U.S. Pat. No. 3,838,346 to Cox (1974) describes a sample-and-hold circuit designed to be directly responsive to a bipolar input signal without direct current offset utilizing the holding capacitor for low-pass filtering. An operational amplifier and a pair of diodes respond to the input signal and conduct, respectively, when it has a positive slope, while another amplifier and pair of diodes respond and conduct when the input signal has a negative slope. The sampled signal is held on a capacitor for the duration of a holding period and leakage of the capacitor is prevented by the two pairs of diodes that are rendered nonconducting during the holding period.
U.S. Pat. No. 4,370,572 to Cosand et al. (1983) shows a sample-and-hold circuit in which analog signals are processed differentially in order to minimize errors inherent in single-ended processing. The circuit comprises two input amplifiers providing a differential analog signal on a pair of analog signal lines connected to a pair of holding capacitors, a differential output amplifier having inputs coupled to these capacitors and providing a sampled analog output signal, and switching means for selectively coupling the analog signal lines to the pair of holding capacitors. Because of the differential processing of the analog signal, errors due to input currents drawn by the output amplifier are cancelled in a properly balanced circuit, since such currents tend to increase or decrease the charge on both capacitors. Similarly, any switching energy coupled to one of the holding capacitors while in the hold mode tends to be counteracted by a balancing energy coupled to the other holding capacitor.
In U.S. Pat. No. 4,779,012 (1988), Moscovici teaches a track-and-hold amplifier having an additional switching means to add compensatory signals to a second input of an operational amplifier used in the system in order to counteract undesirable effects of the operational amplifier's first input. The result is a circuit with shorter settling times and correspondingly higher conversion frequencies for analog-to-digital apparatus.
U.S. Pat. No. 4,806,790 to Sone (1989) illustrates a sample-and-hold device with a clamping circuit to keep the voltage level of the holding capacitor at a constant value during the hold mode. This is achieved by keeping the base node of the charging transistor at a predetermined value by voltage clamping means operative to cause that transistor to be turned off. Thus, the capacitor supplies a base current only to the driving transistor, thereby decreasing the driftage of voltage at the output node.
Finally, in U.S. Pat. No. 4,845,382 (1989), Eouzan et al. illustrate a sample-and-hold device wherein two identical and parallel sample-and-hold circuits are coupled to a differential amplifier. The signal to be sampled is applied at the input of the first sample-and-hold circuit, while a direct electrical voltage is applied to the input of the other, and both are controlled by the same control pulses. The result is that the sampled signal given at the output of the differential amplifier is a pure signal, net of the interference sampling signals given by the first sample-and-hold circuit.
Thus, there still exists a need for a track-and-hold apparatus with a minimum number of components and low complexity for higher speed, better accuracy, low quiescent power, and low cost implementation. The new topology described herein is directed at attaining these results.